Memory architecture for a multiple format video signal processor
US6900845B1 · kind B1 · utility
19Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1997 |
| Grant date | May 31, 2005 |
| Priority date | — |
| Expiry date | Apr 7, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/4621
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A video decoder transcodes video data from various input formats to a predetermined output format. Input data may be standard definition data or MPEG2 compressed data. Standard definition data are rearranged into block format to be compatible with the decoder's single display processor. The display processor selectively processes and conveys either MPEG2 format data or non-MPEG2 format data to a display device. A block based frame memory stores MPEG2 and non-MPEG2 pixel block data, as well as standard definition data in raster line format during processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.