Scan chain testing of integrated circuits with hard-cores

US6901544B1 · kind B1 · utility

Assignee

• LSI Logic Corporation · US

Inventors

• Joerg Huth · Unterföhring, DE
• Andreas Hils · Unterhaching, DE

Key dates

• Filing date: Oct 24, 2001
• Grant date: May 31, 2005
• Expiry date: Apr 2, 2023

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318544
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

The invention relates to an integrated circuit including a hard-core and a peripheral circuit. The hard-core and the peripheral circuit each include respective registers, which are couplable for scan chain testing by respective scan chain paths within the core and within the peripheral circuit. In order to avoid timing problems between the two scan chain paths, a lock-up latch is provided within the hard-core. The lock-up latch has an input coupled to the last register in the scan chain path within the hard-core, and an output coupled to the first register in the scan chain path in the peripheral circuit. The lock-up latch forms part of the hard-core and is clocked by the same clock signal as the last register in the hard-core scan chain path.