Method for making MOSFET anti-fuse structure
US6902958B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2004 |
| Grant date | Jun 7, 2005 |
| Priority date | — |
| Expiry date | Feb 9, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.