Magnetic sensor integrated with CMOS
US6903429B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2003 |
| Grant date | Jun 7, 2005 |
| Priority date | — |
| Expiry date | Jul 24, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N52/101
Abstract
A magnetic sensor device formed using SOI CMOS techniques includes a substrate, a silicon oxide layer and in some cases a plurality of gated regions. A first terminal is located between two innermost gated regions and supplies a supply voltage. A second and a third terminal, each of which is located between two adjacent gated regions other than the two innermost gated regions, output positive and negative Hall voltages. By appropriately controlling a bias voltage to the gated regions, small changes in a magnetic field induces larger currents in channel regions under the gated regions, which, in turn, results in detectable Hall voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.