Pipelined low-voltage current-mode logic with a switching stack height of one
US6903579B2 · kind B2 · utility
6Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2003 |
| Grant date | Jun 7, 2005 |
| Priority date | — |
| Expiry date | Jul 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1738
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Multiple-input CML gates with a stack height of one are provided by using a composite device wherein input signals are propagated to the output through two or more stages of CML-like primitives connected in succession. A universal three-input CML gate (a 2:1 multiplexor) is provided by using a two-stage pipeline, and can be used to build other logic devices, such as AND, OR, and XOR functions, or a latch. The pipelined CML gates with a stack height of one provide a substantially improved voltage-speed trade-off under low-voltage conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.