Circuit and method for cancellation of column pattern noise in CMOS imagers
US6903670B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2003 |
| Grant date | Jun 7, 2005 |
| Priority date | — |
| Expiry date | Oct 6, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/123
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method measure the output voltage of a CMOS pixel in a manner that substantially reduces all columnar pattern noise due to mismatches in the signal processing circuits including the correlated double sampling amplifiers and A/D converters. The circuit includes a test switch, operatively connected between a reference voltage source and a correlated double sampling amplifier, for applying a test voltage from the reference voltage source when the state of the test switch is ON to the correlated double sampling amplifier. The reference voltage source produces a voltage corresponding to a full-scale voltage level to enable the determination of a gain error in the correlated double sampling amplifier and/or A/D converter; a voltage corresponding to ground to enable the determination of an offset error in the correlated double sampling amplifier and/or A/D converter; and a plurality of analog voltages ranging from analog ground to a full-scale voltage level to enable the determination of non-linearity errors in the A/D converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.