Semiconductor memory device
US6903956B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 26, 2003 |
| Grant date | Jun 7, 2005 |
| Priority date | — |
| Expiry date | Sep 26, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One semiconductor memory device according to the invention comprises a plurality of memory blocks, signal lines respectively connected to the plurality of memory blocks, and a control circuit connected to the signal lines, and the control circuit includes selection signal generator circuits for generating selection signals for selecting one memory block of the plurality of memory blocks by externally input address signals and for outputting the selection signals to the signal lines, and the lengths of the signal lines from the selection signal generator circuits to the respective memory blocks are longer in proportion to distances from the control circuit to the memory blocks. Thereby, parasitic load capacitances of the signal lines connected to the respective memory blocks in the wiring direction can be reduced, and the semiconductor memory device that operates with lower current consumption can be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.