Self-route multi-memory packet switch adapted to have an expandable number of input/output ports
US6904046B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2001 |
| Grant date | Jun 7, 2005 |
| Priority date | — |
| Expiry date | Mar 26, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/506
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Data transmission system comprising a plurality of Local Area Networks (LANs) (10-1 to 10-4) interconnected by a hub (12) including the same plurality of LAN adapters (16-1 to 16-4) respectively connected to the LANs and a packet switch (14) interconnecting all LAN adapters wherein a packet transmitted by any adapter to the packet switch includes a header containing at least the address of the adapter to which the packet is forwarded. At each cross point is located a memory block for storing any data packet received from the input port corresponding to the cross point and which is to be forwarded to the output port corresponding to the cross point. The packet switch is composed of N×N identical packet switch modules with each of the packet switch modules being associated with m input ports and m output ports and comprises a rank selector which is programmed to provide a rank k from 0 to N−1 to each column of N modules corresponding to the same output ports, this rank being provided to all memory blocks of the column in order to shift the physical address of each output port in the column by an offset of k×m.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.