Method and circuit for setup and hold detect pass-fail test mode
US6904551B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 20, 2001 |
| Grant date | Jun 7, 2005 |
| Priority date | — |
| Expiry date | May 3, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit thereof for performing setup and hold (SUAH) testing on integrated circuits including, but not limited to SRAM, utilizing a relatively low number of test vectors, obviating the conventional requirement of writing to and reading back from each and every memory address. In one embodiment, a first test data signal of all zeros (0) is inputted to the input stage of the SRAM under test, and a subsequent second data signal of all ones (1) follows. In one embodiment, XOR/XNOR gates detect differences in data signals between the inputs and outputs of input stage latches/registers after clocking. In one embodiment, detected differences are combined into an error signal in combinational logic. In one embodiment, error signals are exported serially to a test system by a scan chain. Alternatively, in another embodiment, error signals are exported in parallel via individual output drivers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.