Patent · US Expired

Solution processed devices

US6905906B2 · kind B2 · utility

25Cited by

5References

73Claims

0Family size

Assignee

PLASTIC LOGIC LIMITED · GB

Inventors

Henning Sirringhaus · Cambridge, GB
Takeo Kawase · Suwa, JP
Richard Henry Friend · Cambridge, GB

Key dates

Filing date	Jun 21, 2002
Grant date	Jun 14, 2005
Priority date	—
Expiry date	Jun 21, 2022

Classification

Technology area (CPC H)Electricity
CPC primaryH10K71/30
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method for forming a transistor, comprising: depositing a first material from solution in a first solvent to form a first layer of the transistor, and subsequently whilst the first material remains soluble in the first solvent, forming a second layer of the transistor by depositing over the first material a second material from solution in a second solvent in which the first material is substantially insoluble.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.