Method for improving planarity of shallow trench isolation using multiple simultaneous tiling systems
US6905967B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 31, 2003 |
| Grant date | Jun 14, 2005 |
| Priority date | — |
| Expiry date | Jun 23, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76229
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a feature layer of a semiconductor wafer, dummy tiles which overcome the tendency of dishing and erosion to occur during a CMP process are placed with various sizes and in various positions. An isolation zone is provided around active features. A scanning process of the feature layout surveys oxide density and nitride density over the wafer layer outside of said isolation zone. Values of the ratios of oxide/nitride density for two or more length scales which define tiling zones, are calculated. Tile placement and sizing in the zones is dependent upon the oxide/nitride density ratio values; and further upon an oxide deposition model specific to the oxide used in the fabrication process and upon a polishing model of the CMP process being employed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.