High dynamic linearity current-mode digital-to-analog converter architecture
US6906652B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 2, 2003 |
| Grant date | Jun 14, 2005 |
| Priority date | — |
| Expiry date | Sep 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/747
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention dramatically reduces dynamic mismatches between the different current segments of a segmented current-mode DAC. By providing substantially the same local architecture for each of the individual current segments, parasitic effects of any physical realization can be controlled. In one embodiment, the most-significant-bit (MSB) current segments and the least-significant-bit (LSB) current segments each have the same number of multiple internal current branches. In the MSB segments, the multiple internal current branches are combined at a source node; whereas, in the LSB segment, a portion of the segment current is dumped, or wasted, through at least some of the internal current branches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.