Magnitude comparator
US6907443B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 19, 2001 |
| Grant date | Jun 14, 2005 |
| Priority date | — |
| Expiry date | Jul 7, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A magnitude comparator circuit may include a first circuit coupled to receive the operands to be compared, a second circuit coupled to the first circuit, and a third circuit coupled to the second circuit and coupled to receive a first operand of the operands to be compared. The first circuit is configured to generate a vector indicative of whether or not bits in the first operand and the second operand are equal. The second circuit receives the vector, and generates an indication of the first bit, beginning with the most significant bit, at which the first operand and the second operand differ. The third circuit receives the indication, and generates an indication of whether or not the first operand is greater than the second operand. In one embodiment, the first, second, and third circuits are included in a combined magnitude compare/count leading zero circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.