Data processing system with master and slave processors
US6907454B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2000 |
| Grant date | Jun 14, 2005 |
| Priority date | — |
| Expiry date | Apr 19, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system comprises a master processor (10), a slave processor (30), a memory (50), and a bus subsystem (20) interconnecting the master processor (10), the slave processor (30), and the memory (50). The master processor (10) is configured to generate, in response to a memory access instruction, a read request comprising a read command for execution by the slave processor (30) to read data stored in a location in the memory (50) specified by the memory access instruction, and to write the read request to the slave processor (30) via the bus subsystem (20). The slave processor (30) is configured to execute the read command received in the read request from the master processor (10) to obtain the data stored at the specified location in the memory (50) and to write the data thus obtained to the master processor (10) via the bus subsystem (20).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.