Reducing transitions on address buses using instruction-set-aware system and method
US6907511B2 · kind B2 · utility
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Key dates
| Filing date | Jan 14, 2003 |
| Grant date | Jun 14, 2005 |
| Priority date | — |
| Expiry date | Oct 24, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction-set-aware method for reducing transitions on an irredundant address bus comprises receiving a first address for communication to a memory on an irredundant address bus. The method retrieves an instruction from a memory location indicated by the first address, transmits the instruction on a data bus, and determines a category of the instruction. The method predicts a second address based, at least in part, on the first address, the instruction, and the category of the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.