System for recovering received data with a reliable gapped clock signal after reading the data from memory using enable and local clock signals
US6907541B1 · kind B1 · utility
9Cited by
10References
44Claims
0Family size
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Key dates
| Filing date | Nov 7, 2000 |
| Grant date | Jun 14, 2005 |
| Priority date | — |
| Expiry date | Sep 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for reliably receiving data includes a memory, write logic, and read logic. The write logic receives data and an unreliable clock signal and writes the data to the memory using the unreliable clock signal. The read logic generates a gapped clock signal and reads the data from the memory using the gapped clock signal. The read logic generates the gapped clock signal by turning on and off a constant local clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.