Tunable sidewall spacer process for CMOS integrated circuits

US6908800B1 · kind B1 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Youngmin Kim · Yongin-si, KR
• Shawn T. Walsh · Richardson, US

Key dates

• Filing date: May 18, 2000
• Grant date: Jun 21, 2005
• Expiry date: May 18, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0184

Abstract

A mixed voltage CMOS process for high reliability and high performance core transistors and input-output transistors with reduced mask steps. A gate stack (30) is formed over the silicon substrate (10). Ion implantation is performed of a first species and a second species to produce the doping profiles (70, 80, 90, 100) in the input-output transistors.