Method for manufacturing semiconductor device and apparatus for manufacturing thereof
US6908860B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2003 |
| Grant date | Jun 21, 2005 |
| Priority date | — |
| Expiry date | Jun 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
The object of the invention is to provide a method of manufacturing a semiconductor device and a processing apparatus for planarization wherein to form copper wiring in multiple layers. The removal of a residue of polishing by local electro polishing, the enhancement of the performance of planarization by using a grindstone and the reduction by small frictional force in electro polishing of damage, are enabled. To achieve the object, the following measures are taken. A residue of polishing of copper is removed by combining the detection of a local area including the residue of polishing of copper and local processing for electro polishing. As small-load processing for planarization is enabled by using electro polishing, multilayer interconnection structure using low-k material as a dielectric interlayer is also enabled. Plural pairs of small unit electrodes in a pair of which minus electrodes surround a plus electrode are provided to a tool for electro polishing, each electrode is connected to a power supply, pulse voltage is applied to each electrode and copper is electrolytically polished.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.