Mixed signal integrated circuit with improved isolation
US6909150B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 23, 2001 |
| Grant date | Jun 21, 2005 |
| Priority date | — |
| Expiry date | Sep 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having improved isolation includes a first circuit section formed in a substrate and a second circuit section formed in the substrate, the second circuit section being spaced laterally from the first circuit section. The integrated circuit further includes an isolation buried layer formed under at least a portion of the first circuit section, and a conductive layer formed on a surface of the substrate and electrically coupled to the buried layer and to a voltage reference, the conductive layer reducing an effective lateral resistance of the buried layer, whereby an isolation between the first and second circuit sections is increased. A second isolation buried layer can be formed under at least a portion of the second circuit section as well to provide further isolation between the first and second circuit sections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.