Flip-flop circuit
US6909314B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 15, 2003 |
| Grant date | Jun 21, 2005 |
| Priority date | — |
| Expiry date | Aug 15, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flip-flop circuit includes a master latch and a slave latch, where a latch operation of the slave latch is controlled by a comparison result between an output signal of the master latch and an output signal of the slave latch. For example, a master latch gate receives an input signal and outputs the input signal under control of a clock signal and an inverted clock signal. A master latch receives the signal output by the master latch gate and latches the signal output by the master latch gate under control of the clock signal and the inverted clock signal. A slave latch gate receives the signal latched by the master latch and outputs the signal latched by the master latch under control of the clock signal and the inverted clock signal. A slave latch receives the signal output by the slave latch gate and latches the signal output by the slave latch gate under control of a slave latch control signal and an inverted slave latch control signal. A comparator receives the signal output by the master latch, an inverted signal of the signal output by the master latch, the signal output by the slave latch and an inverted signal of the signal output by the slave latch, and generates the sl…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.