Variable delay circuit with high resolution
US6909316B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2003 |
| Grant date | Jun 21, 2005 |
| Priority date | — |
| Expiry date | Feb 21, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/265
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Variable delay circuits and methods for delaying a waveform by an adjustable time delay are disclosed herein. One such variable delay circuit comprises a delay range limitation circuit having a first differential input, a first differential output, and a second differential output. The first differential input is configured to receive an input waveform. The first differential output is configured to output the waveform with a maximum delay, and the second differential output is configured to output the waveform with a minimum delay. The variable delay circuit further comprises a delay mixing circuit having second and third differential inputs, first and second control inputs, and a third differential output. The second differential input is connected to the first differential output. The third differential input is connected to the second differential output. The first and second control inputs are configured to receive control voltages V1 and V2, which are related to a selected time delay. The differential output is configured to output the waveform with the selected time delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.