Fractal sequencing schemes for offset cancellation in sampled data acquisition systems
US6909388B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2004 |
| Grant date | Jun 21, 2005 |
| Priority date | — |
| Expiry date | Jun 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/438
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to the isolation and cancellation of the offset voltage component typically experienced at the input of sampled-data analog systems. In an exemplary embodiment, offset isolation and cancellation may be performed during normal operation of the sampling circuitry. In an exemplary embodiment, the present invention combines a front-end switching topology with one or more differential integrator stages and a logic algorithm implemented in the differential integrator stages. In operation, the circuitry preferably performs a number of samples for each stage, applies an inversion factor to the samples in accordance with the algorithm and integrates the samples to effect the cancellation of the offset voltage without substantially affecting the sampled input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.