Method and apparatus for calibration of an array of scaled electronic circuit elements
US6909389B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2002 |
| Grant date | Jun 21, 2005 |
| Priority date | — |
| Expiry date | Mar 24, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/74
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for calibrating an electronic circuit which required scaled matching of some or all of its electronic components with nonvolatile programmably trimmable parameter sources (current, voltage, resistance, capacitance) is carried out in a top-down (highest order bit first, lowest order bit last) fashion without an analog division step. The method and apparatus are applicable, for example, to current-steering digital-to-analog converters (DACs), voltage-controlled oscillators (VCOs), voltage-steering DACs, and the like. In each of these applications the method and apparatus is used to match successive device outputs according to a desired scale factor, proceeding top-down from large output devices to smaller output devices, thereby successively shrinking the cross-device errors which accrue during the matching process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.