Cluster based redundancy scheme for semiconductor memories
US6909645B2 · kind B2 · utility
8Cited by
7References
24Claims
0Family size
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Key dates
| Filing date | Jul 16, 2002 |
| Grant date | Jun 21, 2005 |
| Priority date | — |
| Expiry date | Jul 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, a cluster redundancy scheme may be implemented. Such a scheme may provide cluster segments including rows and columns of replacement memory elements to selectively replace defective elements arranged in rows, columns, or blocks in a main memory array of a semiconductor memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.