Chip to chip interface for interconnecting chips
US6910092B2 · kind B2 · utility
43Cited by
10References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2001 |
| Grant date | Jun 21, 2005 |
| Priority date | — |
| Expiry date | Mar 30, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4265
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure. Communications between the chips are provided by a pair of Chip to Chip Macros, one of each operatively positioned on one of the chips, and a Chip to Chip Bus Interface operatively coupling the Chip to Chip Macros.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.