Method and apparatus for invalidation of data in computer systems
US6910107B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 23, 2000 |
| Grant date | Jun 21, 2005 |
| Priority date | — |
| Expiry date | Sep 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems consistent with this invention conserve computer resources in a hierarchical memory system by preventing scratch data from unnecessarily being copied from a lower hierarchy to a higher hierarchy storage space. Such methods and systems invalidate portions of data in the higher hierarchy storage space so that the coherence protocol does not copy the data to the lower hierarchy storage space. For example, methods and systems consistent with this invention hierarchically store data in a computer system having a main memory and a cache memory. Such methods and systems designate an area of the cache memory that contains scratch data as invalid, wherein the invalid data occupies less space than a maximum space of the cache memory, and permit a writing over of the invalid data in the cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.