Interface layer for the fabrication of electronic devices
US6911385B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2002 |
| Grant date | Jun 28, 2005 |
| Priority date | — |
| Expiry date | Aug 22, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/0241
Abstract
The present invention is directed to methods for making electronic devices with a thin anisotropic conducting layer interface layer formed between a substrate and an active device layer that is preferably patterned conductive layer. The interface layer preferably provides Ohmic and/or rectifying contact between the active device layer and the substrate and preferably provides good adhesion of the active device layer to the substrate. The active device layer is preferably fashioned from a nanoparticle ink solution that is patterned using embossing methods or other suitable printing and/or imaging methods. The active device layer is preferably patterned into an array of gate structures suitable for the fabrication of thin film transistors and the like.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.