Reducing reset noise in CMOS image sensors
US6911640B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2003 |
| Grant date | Jun 28, 2005 |
| Priority date | — |
| Expiry date | Nov 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/626
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An exemplary CMOS image sensor comprises a reset transistor, a photodiode, reset drain voltage circuitry, and reset gate voltage circuitry. A cathode of the photodiode is connected to a source of the reset transistor, and an anode of the photodiode is connected to ground. The reset drain voltage circuitry is connected to a drain of the reset transistor, and the reset gate voltage circuitry is connected to a gate of the reset transistor. During an exemplary hard reset operation, the reset drain voltage circuitry supplies a first drain voltage to the drain of the reset transistor in accordance with a determined level of light for exposure, which is determined dynamically. According to another exemplary reset operation, a hard reset phase is immediately followed by a soft reset phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.