Semiconductor integrated circuit
US6911850B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 14, 2002 |
| Grant date | Jun 28, 2005 |
| Priority date | — |
| Expiry date | Jun 2, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a semiconductor integrated circuit including a phase comparison circuit for a DLL in a reception circuit for receiving serial digital transmission signals, phase detection characteristics of the phase comparison circuit are improved while preventing false lock so as to improve response speed and locking accuracy of the DLL as a whole. The semiconductor integrated circuit includes series-connected delay elements each having a delay time which is controlled in accordance with a control voltage, a phase comparison circuit for generating a voltage corresponding to a phase difference between a clock signal input to a predetermined one of the delay elements and a clock signal output from another predetermined one of the delay elements, a control circuit for controlling the phase comparison circuit to generate a predetermined voltage when said phase difference is within a predetermined range, and a filter circuit for filtering the voltage generated by the phase comparison circuit to generate the control voltage to be applied to the delay elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.