Circuit with voltage clamping for bias transistor to allow power supply over-voltage
US6911871B1 · kind B1 · utility
3Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2003 |
| Grant date | Jun 28, 2005 |
| Priority date | — |
| Expiry date | Mar 13, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0322
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A ring oscillator stage includes two differential transistor pairs configured to add an adjustable amount of delay to a differential input signal. Each differential pair is biased with a bias current transistor; the bias current transistor is “protected” by a voltage-clamping transistor that limits the drain voltage of the bias current transistor. The voltage-clamping transistors enable use of a power supply voltage (VDD) that would otherwise exceed the reliability breakdown voltage limit of the bias current transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.