System clock synchronization using phase-locked loop
US6912260B2 · kind B2 · utility
2Cited by
7References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2002 |
| Grant date | Jun 28, 2005 |
| Priority date | — |
| Expiry date | Feb 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An apparatus for synchronizing the system clocks of wireless devices in a digital communications system is presented. A digital phase-locked loop is employed. The phase-locked loop may include a counter which is incremented by a local device system clock and latched by a frame synchronization marker received from a remote device, whereby the counter output comprises a feed forward signal. The phase-locked loop may alternatively include a counter that reflects the level of data stored in receive and/or transmit FIFO buffers. The loop output signal controls the frequency of the system clock oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.