Bus analyzer unit with programmable trace buffers
US6912673B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 1, 2002 |
| Grant date | Jun 28, 2005 |
| Priority date | — |
| Expiry date | Sep 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Bus Analyzer Unit (BAU) for performing trace analysis on either or both the global bus (GBus) or the I/O bus of a semiconductor chip. The BAU has a GBus trace unit and an I/O bus trace unit, each with its own trace logic. Each unit has filters and comparators which determine what data is recorded and when it is recorded. Trace data recorded by the units is written to a programmable, circular trace buffer in local memory or an SDRAM. Each trace unit has two registers holding the start and end addresses of the trace buffer. Each unit has a next address register containing the next address to which data may be written. As data is written, the next address register is incremented. When the next address register equals the value in the end address register, the next address register is reloaded with the address in the start register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.