Mechanism to avoid explicit prologs in software pipelined do-while loops
US6912709B2 · kind B2 · utility
7Cited by
4References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2000 |
| Grant date | Jun 28, 2005 |
| Priority date | — |
| Expiry date | Nov 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a mechanism that facilitates speculative execution of instructions within software-pipelined loops. In accordance with one embodiment of the invention, a software-pipelined loop is initialized with a speculative instruction deactivated. At least one initiation interval of the software-pipelined loop is executed, and the speculative instruction is activated. Subsequent initiation intervals of the software-pipelined loop are then executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.