Method of making a lead-on-chip device
US6913951B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2003 |
| Grant date | Jul 5, 2005 |
| Priority date | — |
| Expiry date | Jan 14, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device which is sealed with a plastic sealing layer and whose thickness is regulated to be below a given value is known. Since the thickness of the device is small, and the thickness of the upper portion of the plastic sealing layer and the thickness of the lower portion thereof are different from each other, the plastic sealing layer becomes warped, thus causing a crack on the side of the semiconductor chip.To solve this problem, the semiconductor device according to the present invention comprises a semiconductor chip on which a plurality of grooves are defined. Consequently, the thickness of the lower portion of the plastic layer becomes greater, thereby preventing cracks from occurring on the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.