Method and apparatus for controlling a dual-slope integrator circuit to eliminate settling time effect
US6914471B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2003 |
| Grant date | Jul 5, 2005 |
| Priority date | — |
| Expiry date | Dec 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1534
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a method and apparatus for controlling a dual-slope integrator circuit, a reset signal is provided to a reset input of the integrator circuit to maintain a reset state of an integrating capacitor for a predetermined reset time period in response to an original input signal. A delayed input signal is simultaneously generated by introducing a predetermined delay period into the original input signal, the delay period being longer than the reset time period. With reference to the original input signal and the delayed input signal, a trigger signal is provided to an integrator input of the integrator circuit for enabling charging operation of the integrating capacitor during a charging period that starts from the end of the reset time period and that terminates at a lagging edge of the delayed input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.