Differential amplifier with DC offset cancellation
US6914479B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2003 |
| Grant date | Jul 5, 2005 |
| Priority date | — |
| Expiry date | Aug 1, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45652
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is disclosed an improved differential amplifier (20) having a feedback loop that generates an amplified output signal (Vout) from an input signal (Vin) supplied by a preceding stage. It comprises an input matching circuit (11) connected to said preceding stage, a buffer (22) and an amplification section (12) connected in series in the direct amplification line, a first amplifier (16), a RC network (17′) and a second amplifier (23) connected in series in a parallel loop between the outputs and the inputs of the amplification section that generate the feedback signal. The role of said buffer and second amplifier associated in a dedicated direct and feedback signal combining block (21) is to respectively isolate the input signal and the feedback signal from the summing nodes (A′,B′) at the amplification section inputs. As a result, the summation of the input signal and the feedback signal is improved, the DC component of the output signal is filtered out in order to significantly reduce the DC offset. In addition, the input impedance matching represented by parameter S11 is considerably improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.