Clamping circuit for an RF receiver system
US6914522B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2003 |
| Grant date | Jul 5, 2005 |
| Priority date | — |
| Expiry date | Jul 13, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG07C2009/00373
- WIPO fieldTransport
- WIPO sectorMechanical engineering
Abstract
A low power consumption RF receiver system that is adapted for receiving and shaping transmitted digital data signals into a digital data stream for processing by a microprocessor is provided. The receiver system comprises an integrated circuit, which includes a data slicer adapted to accept the received digital data signals, shape the signals into a digital data stream, and pass the digital data stream to the microprocessor. The integrated circuit further includes a peak detector adapted to sense ambient circuit noise when digital data signals are not present, develop a voltage reference signal representative of the peak value of the ambient circuit noise, and pass the voltage reference signal to the data slicer. The receiver system further includes a support circuit between the peak detector and the data slicer that has a voltage divider and a charge capacitor that is adapted to accept the voltage reference signal and produce a clamping reference for the data slicer thereby preventing the data slicer from responding to ambient circuit noise and passing false digital data streams to the microprocessor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.