Low-power semiconductor memory device
US6914803B2 · kind B2 · utility
15Cited by
6References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2003 |
| Grant date | Jul 5, 2005 |
| Priority date | — |
| Expiry date | Sep 29, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.