Non-volatile semiconductor memory that is based on a virtual ground method
US6914824B2 · kind B2 · utility
1Cited by
3References
8Claims
0Family size
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Key dates
| Filing date | Mar 21, 2003 |
| Grant date | Jul 5, 2005 |
| Priority date | — |
| Expiry date | Mar 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory that prevents a decrease in margin at read time. A bit line in a floating state between a drain in a memory cell to be read and a charged bit line is charged for a certain period of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.