Multiplier capable of multiplication of large multiplicands and parallel multiplications of small multiplicands
US6915322B2 · kind B2 · utility
25Cited by
12References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 4, 2001 |
| Grant date | Jul 5, 2005 |
| Priority date | — |
| Expiry date | Feb 11, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/523
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multiply unit uses four multipliers independently to perform for four parallel multiplications of single-width operands or uses the four multiplier cooperatively with an adder to perform a multiplication of double-width operands. In alternative embodiments, the adder operates in the same clock cycle as the multipliers or in a following clock cycle. Operand selection logic selects pairs of either single-width multiplicands or single-width partial multiplicands depending on for single or double-width multiplies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.