Modular and scalable system bus structure
US6915369B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1999 |
| Grant date | Jul 5, 2005 |
| Priority date | — |
| Expiry date | Jun 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/125
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A high-bandwidth data transfer apparatus that is suitable for modular and scalable processing systems is disclosed. In one embodiment, the data transfer apparatus includes a local bus between each of several processing devices and associated memory modules. The local busses are each coupled to a cross-bus through a bus bridge that consists of multiplexers to steer address and data signals from a local bus along the cross-bus to another local bus. The multiplexer structure of the bridges allows the cross-bus to be dynamically divided into segments in any suitable manner to support multiple concurrent links over the cross-bus. A controller is provided to set the multiplexers in accordance with transfer requests that it receives from the various processing devices. The transfer requests may be of various types such as: single transfer, block transfer, and/or message transfer. The controller may include a request queue for each type of transfer request. The controller may also include a direct memory access controller (DMA) for facilitating the block transfers, and may further include an interrupt controller for notifying the processing devices of various events such as: receipt of a m…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.