Semiconductor memory device
US6917072B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2003 |
| Grant date | Jul 12, 2005 |
| Priority date | — |
| Expiry date | Mar 24, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/69
Abstract
A semiconductor memory device comprises a first conductivity type semiconductor region, a second conductivity type source and drain regions provided in the semiconductor region, a gate insulating film structure provided on the semiconductor region between the source region and drain region and including a first insulating film, a charge accumulation layer and a second insulating film, the charge accumulation layer being selected from a silicon nitride film, a silicon oxynitride film, an alumina film and a stacked film of these films, a control gate electrode provided on the second insulating film, a gate sidewall provided on a side of the control gate electrode and having a thickness thinner than that of the second insulating film in the center of the control gate electrode, a third insulating film provided above the control gate electrode, and a fourth insulating film provided to cover the gate electrode sidewall and the third insulating film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.