Method and apparatus for level shifting
US6917236B2 · kind B2 · utility
5Cited by
19References
2Claims
0Family size
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Key dates
| Filing date | Mar 10, 2004 |
| Grant date | Jul 12, 2005 |
| Priority date | — |
| Expiry date | Mar 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0289
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level-shifter architecture with high-voltage driving capability and extremely low power consumption, exploiting dynamic control of the charge on the gate electrodes of the high-voltage output transistors, is provided. The architecture can be integrated in CMOS technology and can be applied to various applications, including monolithic integration of high-voltage display driver circuits in battery-powered applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.