Memory controller and method of aligning write data to a memory device
US6917561B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2002 |
| Grant date | Jul 12, 2005 |
| Priority date | — |
| Expiry date | Nov 26, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller for aligning write data and a clock strobe signal provided to a memory device includes a delay line coupled to a local clock input and providing as an output a delayed local clock signal. A first latch circuit receives data to be written to the memory device as an input and has an output coupled to a data input of the memory device. The first latch circuit is clocked by a first one of the local clock signal and the delayed local clock signal and provides in response the write data to the data input of the memory device. A clock strobe generating circuit is clocked by a second one of the local clock signal and the delayed local clock signal. The clock strobe generating circuit has an output coupled to a clock strobe input of the memory device and provides the clock strobe signal to the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.