Memory controller interface with XOR operations on memory read to accelerate RAID operations
US6918007B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2002 |
| Grant date | Jul 12, 2005 |
| Priority date | — |
| Expiry date | Nov 20, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/1054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single read request to a memory controller generates multiple read actions along with XOR/DATUM manipulation of that read data. Fewer memory transfers are required to accomplish a RAID5/DATUM parity update. This allows for higher system performance when memory bandwidth is the limiting system component. In implementation, a read buffer with XOR capability is tightly coupled to a memory controller. New parity does not need to be stored in the controller's memory. Instead, a memory read initiates multiple reads from memory based on an address decode. The data from the reads are multiplied and XOR'd before being returned to the requestor. In the case of a PCI-X requestor, this occurs as a split-completion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.