64-bit single cycle fetch scheme for megastar architecture
US6918018B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2002 |
| Grant date | Jul 12, 2005 |
| Priority date | — |
| Expiry date | Jul 30, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The 64-bit single cycle fetch method described here relates to a specific ‘megastar’ core processor employed in a range of new digital signal processor devices. The ‘megastar’ core incorporates 32-bit memory blocks arranged into separate entities or banks. Because the parent CPU has only three 16-bit buses, a maximum read in one clock cycle through the memory interface would normally be 48-bits. This invention describes an approach for a fetch method involving tapping into the memory bank data at an earlier stage prior to the memory interface. This allows the normal 48-bit fetch to be extended to 64-bits as required for full performance of the numerical processor accelerator and other speed critical operations and functions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.