Method and apparatus for controlling the phase of the clock output of a digital clock
US6918049B2 · kind B2 · utility
25Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2002 |
| Grant date | Jul 12, 2005 |
| Priority date | — |
| Expiry date | Jan 21, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock synthesizer produces an output clock that has a programmable phase offset from the input clock. The clock synthesizer includes an accumulator and an offset adder. The output clock is derived from the offset adder. The offset adder receives a value derived from the accumulator and a selected phase offset value. The phase difference between the non-aligned output clock and the aligned output clock is determined by the phase offset value. The time resolution of the clock synthesizer may be defined by the clock rate of the system and the number of bits used in the offset adder and the accumulator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.