Method and apparatus for exact relative positioning of devices in a semiconductor circuit layout
US6918102B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2003 |
| Grant date | Jul 12, 2005 |
| Priority date | — |
| Expiry date | Jan 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of determining the position of devices in a circuit layout includes defining an array of cells and defining a plurality of device outlines in the array, with each device outline received in at least one cell. A set of size constraints is established that expresses the size of each device. For each column and each row of cells having a plurality of device outlines contained completely therein, the position of one of the device outlines is determined and a constraint is established for each other device outline that expresses its position with respect to the position of the one device outline. A spacing constraint for each pair of adjacent device outlines is established that expresses a spacing therebetween. The foregoing constraints are solved simultaneously and a layout of the device outlines is generated in accordance with the solution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.