Method for producing a multi-chip circuit module including a multi-layered wiring section utilizing a via-on-via structure
US6919226B2 · kind B2 · utility
23Cited by
5References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2002 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | Nov 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/016
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-chip circuit module on which semiconductor chips are loaded and which is provided with circuit patterns, input/output terminals or the like for interconnecting the semiconductor chips. A multi-layered wiring section (2) is formed by respective unit wiring layers (8) to (12) in such a manner that an upper unit wiring layer is layered on a surface-planarized subjacent unit wiring layer and connected to one another by inter-layer connection by a via-on-via structure. A semiconductor chip (6) mounted on this multi-layer wiring section (2) is polished along with the sealing resin layer (7) for reducing the thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.