SRAM cell
US6919647B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2003 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | Dec 28, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A SRAM cell includes double-gated PMOS and NMOS transistors to form a latch and retain a value. The unique MOSFET transistor architecture provides a four terminal device for independent gate control, a floating body device, and a dynamic threshold device. The channel may have a U-shaped cross-sectional area to increase the channel length and gate control. First and second insulating spacers are disposed on opposing sides of the top gate such that the first spacer is between the source and the top gate, and the second spacer is between the drain and the top gate. The source and drain include extensions that extend proximate to the spacers and couple to the channel. The spacers shield the channel from the field effect of the source and drain, and further resist compression of the channel by the source and drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.